1. Field of the Invention
The present invention relates generally to a connection structure of an interconnection and an electron active region such as a doped layer in a semiconductor device and more particularly, to an improvement of the connection structure of an interconnection and an electron active region in a dynamic semiconductor memory device having memory cells of a trench type.
2. Description of the Prior Art
A dynamic semiconductor memory device has been already well-known. FIG. 1 is a block diagram showing an entire structure of the conventional dynamic semiconductor memory device.
Referring to FIG. 1, the dynamic semiconductor memory device comprises an array including a plurality of memory cells which are memory portions, respectively, an X decoder and a Y decoder for selecting addresses of the memory cells, and an input/output interface portion comprising sense amplifiers connected to input/output buffers. The plurality of memory cells are connected to intersections of word lines connected to the X decoder and bit lines connected to the Y decoder, the word lines and the bit lines constituting a matrix. In the above described manner, the above described array is structured.
Description is now made on operation. A memory cell is selected which is connected to an intersection of each of the word lines and each of the bit lines selected by the X decoder and the Y decoder, respectively, in response to a row address signal and a column address signal externally applied, from or to which information is read out or written through the input/output interface portion comprising the sense amplifiers and the input/output buffers.
FIGS. 2A and 2B are diagrams showing a structure of a memory cell in the conventional dynamic semiconductor memory device, where FIG. 2A is a plan view thereof and FIG. 2B is a cross sectional view taken along a line IIB--IIB shown in FIG. 2A.
The conventional dynamic semiconductor memory device comprises a memory cell comprised of a single transistor and a single capacitor, the capacitor comprising a capacitor of a trench structure for high integration density of the memory cell. Referring to FIG. 2B, a trench 3 is formed in a p type silicon substrate 1. An n type diffusion layer 6 is formed on the side surface of the trench 3. An n type diffusion layer 2 is formed around the trench 3 and in the planer surface of the substrate 1. A polysilicon (polycrystalline silicon) layer 8 serving as a cell plate is formed on the bottom surface of the trench and in the upper portions of the n type diffusion layers 2 and 6 through a thin oxide film 7. An isolation oxide film 5 is formed in the bottom portion of the trench 3 and an inversion preventing layer 4 is formed adjacent to and under the isolation oxide film 5. The n type diffusion layers 2 and 6, the polysilicon layer 8 and the thin oxide film 7 interposed therebetween constitute a capacitor for storing information charges.
n type diffusion layers 10 are formed spaced apart from each other, adjacent to the n type diffusion layer 2 and in the planer surface of the substrate 1. Polysilicon 9 serving as a word line is formed over the portion between the n type diffusion layers 10. The polysilicon 9 and the n type diffusion layers 10 constitute an n channel transistor for reading out and writing information charges. The n type diffusion layer 10 is connected to an aluminum interconnectlon 13 serving as a bit line through a contact hole 12. The major surface of the p type substrate 1 and the inside of the trench 3 are covered with an insulating film 11.
Description is now made on operation of the conventional semiconductor memory device shown in FIGS. 2A and 2B.
A voltage is applied to the word line 9, so that the conductivity type of the surface region of the semiconductor substrate 1 immediately under the word line 9 is inverted, whereby a channel is formed between the two n type diffusion layers 10.
When information charges are written, a voltage is applied to the bit line 13. As a result, the charges are carried to the capacitor diffusion layers 2, 6, 7 and 8 from the bit line 13 through the contact hole 12, the one diffusion layer 10, the above described channel and the other diffusion layer 10.
On the other hand, when information charges are read out, the charges are carried from the capacitor diffusion layers 2, 6, 7 and 8 to the bit line 13.
A semiconductor memory device of the same trench type, but having a different shape is described in an article by Nakajima et al., entitled "An Isolation-Merged Vertical Capacitor Cell for Large Capacity DRAM", IEDM, 1984, pp. 240-243. In this case, the positional relation of a word line, a contact hole and the like are also the same as that shown in FIGS. 2A and 2B. In addition the manufacturing method comprises a photolithographic process, similarly to the conventional manufacturing method.
Since the conventional semiconductor memory device has the above described structure, the contact hole 12 and the word lines 9 are formed at the same level. As a result, the planer area occupied by a memory cell is increased.
On the other hand, the contact hole 12 is formed by applying a photolithographic process and an etching process to the insulating film 11 between interconnection layers. In order to use the photolithographic process, a size shift of resist, an offset of alignment and a size shift by etching must be avoided.
As described in the foregoing, in the conventional semiconductor memory device, it was difficult to increase the density of a memory device and provide high integration density thereof.